CS1019F - 数字逻辑设计
Grading
- Homework & Quiz 20%
- Random, with no notification, 4 - 5 times
- Topics from textbook and home assignments
- Class performance
- Project 10%
- Experiments 30%
- Final 40%
- 最终成绩比例由老师在期末决定
Textbook
- Logic and Computer Design Fundamental (Fifth Edition) download(en) | download(cn)
Lab Requirements
- 实验文档 by 瓜豪 (TA)
- 学习 Verilog HDL 语言，熟悉硬件实验平台、实验仪器操作等
- 用 Verilog HDL 语言做仿真实验时，要求先编写好代码
- 严禁抄袭，若被发现两个人都记零分
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